Why Nvidia's AI Chips Depend on ASML's Lithography Machines

Nvidia may design some of the most valuable chips in the world, but a design file cannot answer a chatbot prompt. Someone must turn that design into working transistors, connect the finished silicon to memory, and package it into a system that can be delivered to a data center.

One of the most important machines in that chain is built by a Dutch company: ASML.

ASML does not manufacture Nvidia's finished GPUs. It supplies advanced lithography systems to chipmakers, including the extreme ultraviolet, or EUV, tools that enable crucial fine-patterning steps in leading-edge production.

This distinction reveals a central feature of the AI hardware boom: the companies most visible to customers do not own every capability that makes their products possible.

A processor is a network of dependencies

Consider the journey from architecture to accelerator.

The design company determines the chip's logic and requirements. A semiconductor foundry manufactures patterned silicon wafers through many fabrication steps. Other specialists supply materials, optics, production equipment, high-bandwidth memory, substrates and packaging services.

The resulting processor is then assembled with other components into servers and racks.

A constraint at any of these stages can limit how quickly finished computing capacity arrives. The fact that two suppliers serve the same Nvidia product does not make their businesses interchangeable.

Foundry capacity cannot compensate for a missing advanced packaging step. More packaging capacity cannot substitute for a photolithography system that produces the required features on a wafer.

What the Dutch machine actually does

Lithography projects a patterned image onto a light-sensitive material on the surface of a semiconductor wafer. Subsequent processing turns those patterns into device structures and interconnections.

As leading-edge feature dimensions shrank, conventional wavelengths became increasingly difficult to use economically for the most intricate layers. ASML's EUV systems use light with a wavelength of approximately 13.5 nanometers.

Producing that light is an engineering operation that sounds almost implausible. ASML describes lasers hitting fast-moving microscopic drops of tin, creating a hot plasma that emits EUV light. Its EUV product explanation describes systems generating these events up to 50,000 times per second; that is a light-source process, not the number of chips manufactured per second.

EUV light is absorbed easily by air and conventional optical materials. The system uses high vacuum and carefully engineered multilayer mirrors to steer and focus the light. A wafer stage must move and position material with extraordinary repeatability.

The strategic asset is not a single laser or mirror. It is a coordinated manufacturing system that has taken decades of research, supplier development and factory experience to make productive at scale.

ASML's position is not the same as a monopoly on chips

It is easy to move from the observation that ASML is central to EUV lithography to an exaggerated claim that it controls every process needed to make a semiconductor.

ASML itself notes that EUV is used for particular intricate layers while deep ultraviolet lithography remains necessary for other layers. Deposition, etching, inspection, cleaning, testing and other steps require separate equipment and expertise.

Nor does a tool manufacturer's sales forecast automatically translate into a shipment forecast for Nvidia. Equipment orders, factory utilization, yields and end-product demand operate on different schedules.

ASML's importance is therefore more specific—and more interesting—than the claim that one company can make or break every chip. It is a highly specialized supplier at a narrow, difficult-to-replace stage of leading-edge manufacturing.

The next generation adds a second clock

In July 2026, ASML described a milestone with Intel Foundry: particular Intel 18A layers were using its High-NA EUV technology for a subset of Intel's Core Ultra Series 3 processors.

High numerical aperture optics are intended to improve patterning capability. But this Intel milestone does not show that every advanced foundry has made the same transition, nor that Nvidia's current processors are manufactured using High-NA tools.

Chip technologies spread through qualification, yield learning and individual production choices. A successful demonstration at one manufacturer is a meaningful industrial achievement, not automatic evidence of universal adoption.

For AI chip supply, this matters because the transition to new tools involves investment and risk before it delivers mature manufacturing volume.

Beyond the wafer: the packaging constraint

Even successful fabrication is not the end of the story.

High-performance AI accelerators rely on advanced connections between compute dies, high-bandwidth memory and other components. TSMC's 3DFabric and CoWoS technology material describes approaches to advanced heterogeneous integration that help make these dense systems practical.

Packaging has its own factories, processes and qualification bottlenecks. The economic value of an accelerator can depend on both the transistors produced on the wafer and the memory/interconnect system around those transistors.

This is why an announcement about additional wafer capacity cannot, by itself, establish how many complete AI accelerators will ship. The supply chain has to work as a system.

The economics of a hidden chokepoint

For Nvidia, manufacturing through specialist partners allows enormous focus on architecture, software, platforms and customers without constructing every advanced fab and equipment factory itself.

The price of that focus is dependence on external capabilities. Other chip designers, foundries and semiconductor equipment customers also need scarce engineering talent and capital-intensive manufacturing capacity.

For ASML, being essential to a sophisticated production step can create durable demand. It also creates responsibilities: its customers will judge tools by usable throughput, yield, service reliability and their contribution to chip production economics, not only by technical specifications.

Neither company can treat the other layers of the system as optional.

The paradox of the AI chip race is that software may make an accelerator famous, but building it depends on some of the most stubbornly physical engineering in the world.

The design wins the headline. The manufacturing chain decides when the chip exists.